Based on the working principle, counter structure and Clocked Transmission Gate Adiabatic Logic circuits, a design scheme of decimal counter with reset is proposed. 通过对计数器和钟控传输门绝热逻辑电路工作原理及结构的研究,提出一种带复位功能的低功耗十进制计数器设计方案。
Clocked Quasi-Static Energy Recovery Logic 钟控准静态能量回收逻辑电路
Design of Clocked Transmission Gate Adiabatic Logic Circuit and SRAM 钟控传输门绝热逻辑电路和SRAM的设计